1. Field of the Invention
The present invention relates to an A/D converter unit for an image sensor for converting the output of an analog image from the image sensor into digital data and in particular, an A/D converter unit appropriate for an image sensor having column arrangement.
2. Background of the Related Art
In a digital still camera and a mobile phone camera, conventionally, CCD and APS (active pixel sensor) CMOS image sensors have been in use. In accompany of higher resolution in recent years, the number of pixels tends to be increased. Meanwhile, there are also requirements for high speed continuous shooting, high frame-rate moving images, etc. In combination of the above two, requirement for reading out at high speed is becoming intensified. However, when the increase of the number of pixels or the acquisition of high-speed reading is intended, the number of pixel signals to be read out in a unit time must be increased, needless to say. Therefore, high speed is required in circuits for reading out signals and for converting the readout analog signals into digital signals. In CCD, which has been a mainstream imaging device until now, horizontal CCD has to be driven at high speed to perform high speed reading. This makes it difficult to reduce current consumption. Therefore, recently, the use of the APS CMOS image sensor is increasing. However, even when using the APS CMOS image sensor (hereafter expressed as CMOS image sensor or simply, image sensor), the situation is that, to achieve high speed with maintained high resolution, the increase of current consumption in an A/D converter to convert analog signals into digital signals is inevitable.
As one method to solve the above problem, in case of the CMOS image sensor, because it is easy to integrate CMOS circuits into an identical chip, several methods using a so-called column-parallel A/D converters have been proposed. By use of the column A/D converter, pixel signals from the image sensor are output column-by-column in parallel, and the image signals of each column are converted into digital data simultaneously in parallel.
For example, in the non-patent document 1, a method using a successive approximation A/D converter composed of capacitors is disclosed. According to this method, an A/D conversion circuit is configured of comparator, D/A conversion circuit and successive approximation register. Because high performance operational amplifier is not necessary, the method is suitable for a column A/D converter that requires arrangement with a narrow pitch. The method is highly promising because of high conversion speed also. However, when a general charge-redistribution D/A conversion circuit is used, a plurality of weighted capacitors are to be arranged. For example, in order to perform A/D conversion with the resolution of 10 bits, it is necessary to provide totally 1024 pieces of unit capacitors having 1C to 512C. Therefore, even if fine process will be advanced in future, variation of elements may be increased when the capacitor size is made smaller. This causes deteriorated performance of A/D conversion, and it is not possible to reduce the capacitor area accordingly. Thus, the method has a defect that realization of high resolution is difficult in a column A/D converter requiring a narrow pitch formation.
Also, in the non-patent document 2, there is disclosed a method using a so-called single-slope A/D converter includes a ramp signal generator, a comparator and a counter. This method has merits of being suitable for column arrangement because of the use of a small number of elements, and being achievable without use of an operational amplifier, similar to the aforementioned successive approximation A/D converter. However, to improve the resolution in A/D conversion, a time required for the A/D conversion increases in the manner of an exponential function. This produces a serious demerit of difficulty in obtaining high resolution.
Also, as a column A/D converter, a method using a AZ type is disclosed in the patent document 1, and also, a method using a cyclic type is disclosed in the patent document 2. Both types require high performance operational amplifiers because of requiring highly accurate calculation by switched capacitor circuits. However, it is becoming difficult in recent years to arrange such highly accurate operational amplifiers into columns with a slender-shaped layout to fit to a narrow pixel pitch. The reason is that it is necessary to use transistors manufactured under fine design rules to reduce the layout size. Such a fine transistor has a low voltage tolerance that requires a low power supply voltage, and therefore, it is not possible to ensure enough dynamic range of the operational amplifier.
From the above discussion, when column arrangement with a narrow pitch is taken into consideration, the successive approximation method not necessitating operational amplifiers or the single slope method are left as candidates. From the viewpoint of high speed, the single slope method is extremely difficult. On the other hand, to obtain a multi-bit A/D converter unit using the aforementioned simple charge-redistribution successive approximation A/D converters, an extremely large number of elements are required, which is unsuitable for a column A/D converter having a large restriction in size.
Meanwhile, though it is not a column A/D converter, in the patent document 3, there is disclosed the prior art for obtaining high resolution with a reduced number of elements. FIG. 13 shows the block diagram thereof. A D/A converter for use in successive approximation is divided into an upper level and a lower level. A resistor-string D/A converter is used for the upper-level D/A converter. Also, a so-called charge-redistribution D/A converter, composed of capacitors and switches, is used for the lower-level D/A converter. The respective outputs therefrom are added by the input to a comparator. Thus, a high-resolution, high-speed A/D converter unit with a reduced number of elements is obtained.
However, if it is intended to apply the above-mentioned method intact to a column A/D converter, there are problems described below. One is that, if it is intended to include the resistor string in each column A/D converter, the resistor area is too large to fit in a narrow pitch. The other is that the outputs of the resistor string DAC and the charge redistribution DAC are consequently added by the use of capacitors in the comparator. Therefore, in order to ensure addition accuracy in the upper-level and lower-level D/A converters, it is necessary to make the capacitor size, which is used for the addition in the comparator, sufficiently larger than the capacitor size for use in the second D/A converter, so as to suppress capacitance variation. Further, as shown in FIG. 13, a reference voltage to be input to the second D/A converter is extracted from the both ends (a, b) of one fixed resistor in the resistor string. Therefore, if variation exists in each unit resistor forming the resistor string, the variation leads to the deterioration of a nonlinearity error. To ensure accuracy, the unit resistor size has to be enlarged. This causes a drawback that the overall circuit area becomes large. As such, the method disclosed in the patent document 3 is quite suitable when it will be applied to a single A/D converter having a relatively gentle size restriction. However, it is not suitable for a column A/D converter having a strict restriction of size.
[Preceding Technical Documents]
[Patent Documents]
[Patent document 1] Japanese Unexamined Patent Publication No. 2004-15208.
[Patent document 3] Japanese Unexamined Patent Publication No. 2005-136540.
[Patent document 3] Japanese Unexamined Patent Publication No. Hei-6-152420.
[Non-Patent Documents]
[Non-patent document 1] A. Krymski, D. van Blerktom, A. Andersson, N. Block, B. Mansoorian and E. R. Fossum, “A high speed 500 Frames/s 1024×1024 CMOS Active Pixel Sensor”, 1999 Symposium on VLSI Circuits Digest of Technical Papers pp. 137-138.
[Non-patent document 2] Woodward Yang, Oh-Kwon, Ju-II Lee, Gyu-Tae Hwang and Suk-Joong Lee, “An Integrated 800×600 CMOS Imaging System”, 1999 IEEE Int. Solid State Circuits Conference pp. 304-305, 471.